Ministry: Ministry of Electronics and IT
To train 85,000 qualified engineers in the area of Very-large-scale integration (VLSI) and Embedded System Design.
To develop 175 ASICs (Application Specific Integrated Circuits), Working Prototypes of 20 System on Chips (SoC) and IP Core repository over a period of 5 years.
Participating Institutions: The programme would be implemented at about 100 academic institutions/R&D organisations across the Country (including IITs, NITs, Government/Private Colleges and R&D Organisations). Startups and MSMEs can also participate in the programme by submitting their proposals under Academia- Industry Collaborative Project, Grand Challenge /Hackathons/RFP.
Project Categorization: Under the Chips to Startup (C2S) Programme, based on the Institutions’ expertise, Technology Readiness Level (TRL) and design experience proposals are invited in three different categories:
Design and Development of Systems/SoCs/ASICs/Reusable IP Core
Development of Application Oriented Working Prototype of IPs/ASICs/SoCs and
Proof of Concept oriented Research and Development of ASICs/FPGAs.
Nodal Implementing Agency: C-DAC (Centre for Development of Advanced Computing).
Significance of Chips to Startup (C2S) Programme: The programme will be a step towards the Electronics System Design & Manufacturing (ESDM) space by way of inculcating the culture of SoC/ System Level Design at Bachelors, Masters and Research level and act as a catalyst for the growth of Start-ups involved in fabless design.